# make clean # remove ALL binaries and objectsįor more on makefiles, refer to the GNU Make manual, which offers a complete reference and examples. Below is the rule in its expanded form: foo.o: "Creating object."įinally, we remove all binaries and object files in target clean.īelow is the rewrite of the above makefile, assuming it is placed in the directory having a single file foo.c: # Usage: This is also called a recursive expanded variable, and it is used in a rule as shown below: hello: hello.cĪs you may have guessed, the recipe expands as below when it is passed to the terminal: gcc hello.c -o helloīoth $Įvery prerequisite in the previous rule is considered a target for this rule. For example, to assign the command gcc to a variable CC: CC = gcc The simplest way to define a variable in a makefile is to use the = operator. In the above example, most target and prerequisite values are hard-coded, but in real projects, these are replaced with variables and patterns.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |